Semiconductor device and its manufacturing method capable of reducing low frequency noise

ABSTRACT

In a semiconductor device, a first semiconductor layer is formed on a semiconductor substrate. A second semiconductor layer is formed on a part of the first semiconductor layer, and a third semiconductor layer is formed on a part of the second semiconductor layer. A first electrode is formed on the third semiconductor layer, and a second electrode is formed on the first semiconductor layer in contact with the second semiconductor layer and apart from the semiconductor layer, thus forming a diode.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and itsmanufacturing method, and more particularly, to a diode such as aSchottky barrier diode (SBD), a tunnel diode and a PIN diode and itsmanufacturing method.

[0003] 2. Description of the Related Art

[0004] A first prior art Schottky barrier diode is of a lateral typewhich is constructed by a semi-insulating GaAs substrate, an n⁻-typeGaAs contact layer formed on the GaAs substrate, an n⁺-type GaAs layerformed on the n⁻-type GaAs contact layer, an anode electrode (Schottkyelectrode) formed on the n⁻-type GaAs contact layer, and a cathodeelectrode (ohmic electrode) formed on the n⁺-type GaAs layer. This willbe explained later in detail.

[0005] In the above-described first prior art Schottky barrier diode,however, since the path of the current adjacent to the surface of then⁻-type GaAs contact layer is relatively long and, is also very closethereto, the current is affected strongly by a surface level of then⁻-type GaAs contact layer. As a result, the low frequency noisecharacteristics such as 1/f noise of the Schottky barrier dioderemarkably deteriorates.

[0006] A second prior art Schottky barrier diode is of a vertical typewhich is constructed by a semi-insulating GaAs substrate, an n⁺-typeGaAs contact layer formed on the GaAs substrate, an n⁻-type GaAs layerformed on the n⁺-type GaAs layer, an anode electrode (Schottkyelectrode) formed on the n⁻-type GaAs layer 203, and a cathode electrode(ohmic electrode) formed on the n⁺-type GaAs contact layer (seeJP-A-8-255838). This also will be explained later in detail.

[0007] Thus, in the above-described second prior art Schottky barrierdiode, the path of the current adjacent to the surface of the n⁺-typeGaAs contact layer is shortened, which would improve the low frequencycharacteristics.

[0008] In the second prior art Schottky barrier diode, however, sincethe path of the current adjacent to the surface of the n⁻-type GaAscontact layer is still close thereto, the current is still affectedstrongly by the surface level of the n⁺-type GaAs contact layer. As aresult, the low frequency noise characteristics of the Schottky barrierdiode still deteriorates.

SUMMARY OF THE INVENTION

[0009] It is an object of the present invention to provide asemiconductor device such as a diode and its manufacturing methodcapable of reducing the low frequency noise.

[0010] Another object is to provide such a semiconductor deviceincorporating a heterojunction field effect transistor and aheterojunction bipolar transistor and its manufacturing method.

[0011] According to the present invention, in a semiconductor device, afirst semiconductor layer is formed on a semiconductor substrate. Asecond semiconductor layer is formed on a part of the firstsemiconductor layer, and a third semiconductor layer is formed on a partof the second semiconductor layer. A first electrode is formed on thethird semiconductor layer, and a second electrode is formed on the firstsemiconductor layer in contact with the second semiconductor layer andapart from said the semiconductor layer, thus forming a diode.

[0012] Thus, the current path is distant from the surface level of thesecond semiconductor layer, to improve the low frequency noisecharacteristics.

[0013] Also, the cathode electrode is buried in the first semiconductorlayer so that the current path is further distant from the surface levelof the second semiconductor layer, to further improve the low frequencynoise characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention will be more clearly understood from thedescription set forth below, as compared with the prior art, withreference to the accompanying drawings, wherein:

[0015]FIG. 1 is a cross-sectional view illustrating a first prior artdiode;

[0016]FIG. 2 is a cross-sectional view illustrating a second prior artdiode;

[0017]FIG. 3 is a cross-sectional view illustrating a semiconductordevice to which the diode of FIG. 2 is applied;

[0018]FIG. 4 is a cross-sectional view illustrating a first embodimentof the diode according to the present invention;

[0019]FIGS. 5A through 5E are cross-sectional views for explaining amethod for manufacturing the diode of FIG. 4;

[0020]FIG. 6 is a cross-sectional view illustrating a second embodimentof the diode according to the present invention;

[0021]FIGS. 7A through 7F are cross-sectional views for explaining amethod for manufacturing the diode of FIG. 6;

[0022]FIG. 8 is a cross-sectional view illustrating a third embodimentof the diode according to the present invention;

[0023]FIGS. 9A through 9E are cross-sectional views for explaining amethod for manufacturing the diode of FIG. 8;

[0024]FIG. 10 is a cross-sectional view illustrating a fourth embodimentof the diode according to the present invention;

[0025]FIGS. 11A through 11E are cross-sectional views for explaining amethod for manufacturing the diode of FIG. 10;

[0026]FIG. 12 is a cross-sectional view illustrating a fifth embodimentof the diode according to the present invention;

[0027]FIGS. 13A through 13E are cross-sectional views for explaining amethod for manufacturing the diode of FIG. 12;

[0028]FIG. 14 is a cross-sectional view illustrating a sixth embodimentof the diode according to the present invention;

[0029]FIGS. 16A through 15E are cross-sectional views for explaining amethod for manufacturing the diode of FIG. 14;

[0030]FIG. 16 is a cross-sectional view illustrating a semiconductordevice in which the Schottky barrier diode of FIG. 6 is combined with ahigh electron mobility transistor;

[0031]FIGS. 17A through 1711 are cross-sectional views for explaining amethod for manufacturing the semiconductor device of FIG. 16;

[0032]FIG. 18 is a cross-sectional view illustrating a semiconductordevice in which the Schottky barrier diode of FIG. 6 is combined with aheterojunction bipolar transistor;

[0033]FIGS. 19A through 19I are cross-sectional views for explaining amethod for manufacturing the diode of FIG. 18;

[0034]FIG. 20 is a cross-sectional view illustrating a semiconductordevice in which the Schottky barrier diode of FIG. 6 is combined with ahigh electron mobility transistor and a heterojunction bipolartransistor; and

[0035]FIG. 21 is a cross-sectional view illustrating an epitaxial layerused in the manufacture of the semiconductor device of FIG. 20.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Before the description of the preferred embodiments, prior artdiodes will be explained with reference to FIGS. 1, 2 and 3.

[0037] In FIG. 1, which illustrates a first prior art diode that is, inthis case, a Schottky barrier diode SBD, the Schottky barrier diode SBDis of a lateral type which is constructed by a semi-insulating GaAssubstrate 101, an n⁻-type GaAs contact layer 102 formed on the GaAssubstrate 101, an n⁺-type GaAs layer 103 formed on the n⁻-type GaAscontact layer 102, an anode electrode 104 formed on the n⁻-type GaAscontact layer 102, and a cathode electrode 105 formed on the n⁺-typeGaAs layer 103. Note that a Schottky barrier SB is generated of at aninterface between the anode electrode 104 and the n⁻-type GaAs contactlayer 102.

[0038] In the Schottky barrier diode SBD of FIG. 1, when a forward biasvoltage is applied to the anode electrode 104 and the cathode electrode105, a current as indicated by an arrow I flows from the anode electrode104 to the n⁺-type GaAs layer 103 in parallel with the surface of then⁻-type GaAs contact layer 102, and then, the current I flows from then⁺-type GaAs layer 103 to the cathode electrode 105.

[0039] In the Schottky barrier diode SBD of FIG. 1, however, since thepath of the current I adjacent to the surface of the n⁻-type GaAscontact layer 102 is relatively long, and, is also very close thereto,the current I is affected strongly by a surface level SL of the n⁻-typeGaAs contact layer 102. As a result, the low frequency noisecharacteristics of the Schottky barrier diode SBD of FIG. 1 remarkablydeteriorate.

[0040] In FIG. 2, which illustrates a second prior art diode that is, inthis case, a Schottky barrier diode SBD (see JP-A-8-255838), the Shottkybarrier diode SBD is of a vertical type which is constructed by asemi-insulating GaAs substrate 201, an n⁺-type GaAs contact layer 202formed on the GaAs substrate 201, an n⁻-type GaAs layer 203 formed onthe n⁺type GaAs layer 202, an anode electrode 204 formed on the n⁻-typeGaAs layer 203, and a cathode electrode 205 formed on the n⁺-type GaAscontact layer 202. Note that a Schottky barrier SB is generated at aninterface between the anode electrode 204 and the n⁻-type GaAs layer203.

[0041] In the Schottky barrier diode SBD of FIG. 2, when a forward biasvoltage is applied to the anode electrode 204 and the cathode electrode205, a current as indicated by an arrow I flows from the anode electrode204 to the n⁻-type GaAs layer 203 perpendicular to the surface of then⁻-type GaAs layer 203, and then, the current I flows from the n⁻-typeGaAs layer 203 via the n⁺-type GaAs contact layer 202 to the cathodeelectrode 205 in parallel with the surface of the n⁺-type GaAs contactlayer 202.

[0042] Thus, the path of the current I adjacent to the surface of then⁺-type GaAs contact layer 202 is shortened, which would improve the lowfrequency characteristics.

[0043] In the Schottky barrier diode SBD of FIG. 2, however, since thepath of the current I adjacent to the surface of the n⁻-type GaAscontact layer 202 is still close thereto, the current I is stillaffected strongly by a surface level SL of the n⁺-type GaAs contactlayer 202. As a result, the low frequency noise characteristics of theSchottky barrier diode SBD of FIG. 2 still deteriorate.

[0044] In FIG. 3, which illustrates a semiconductor device to which theSchottky barrier diode SBD of FIG. 2 is applied, a heterojunctionbipolar transistor HBT and a high electron mobility transistor HEMT aswell as the Schottky barrier diode SBD of FIG. 2 are formed in one chip.

[0045] The heterojunction bipolar transistor HBT is constructed by ann⁺type GaAs sub collector layer 206, an n⁻type GaAs collector layer 207,a p⁺-type GaAs base layer 208 an n-type AlGaAs emitter layer 209, ann⁺-type GaAs emitter cap layer 210, collector electrodes 211, baseelectrodes 212 and a collector electrode 213.

[0046] The Schottky barrier diode SBD and the heterojunction bipolar HBTare isolated by a p-type element isolation region 214 formed within then⁺-type GaAs layer 202 and the n⁺-type GaAs layer 206 which are actuallythe same.

[0047] On the other hand, the high electron mobility transistor HEMT isconstructed by a superlattice buffer layer 215, an i-type InGaAs channellayer 216, an n-type silicon planar doped layer 217, an n-type AlGaAslayer donor layer 218, n⁺-type GaAs source/drain layers 219, a T-shapedgate electrode 220, a source electrode 221, and a drain electrode 222.

[0048] When forming the semiconductor device of FIG. 3, an epitaxiallayer for the layers 202, 203, 206, 207, 208, 209 and 210 is grown onthe GaAs substrate 201 by a molecular beam epitaxy (MBE) process. Then,an area of the epitaxial layer for the high electron mobility transistorHEMT is etched by using a mask which covers an area of the opitaxiallayer for the hetro junction bipolar transistor HBT and the Schottkybarrier diode SBD. Then, another epitaxial layer for the layers 215,216, 217, 218 and 219 is regrown on the GaAs substrate 201. Finally,each layer of the epitaxial layers is patterned, and then, eachelectrode is formed to complete the semiconductor device of FIG. 3.

[0049] In the semiconductor device of FIG. 3, however, since anepitaxial layer regrowing process is required, a deep trap level isgenerated at an interface between the n⁻-type GaAs contact layer 202 andthe GaAs substrate 201, which also deteriorates the low frequency noisecharacteristics. Also, the epitaxial layer regrowing process increasesthe manufacturing cost. Further, the characteristics among wafers andamong lots fluctuate, which would decrease the manufacturing yield.

[0050] In FIG. 4, which illustrates a first embodiment of the diodeaccording to the present invention that is, in this case, a Schottkybarrier diode SBD, the Shottky barrier diode SBD is of a vertical typewhich is constructed by a semi-insulating GaAs substrate 1, an n⁺-typeGaAs contact layer 2 formed on the GaAs substrate 1, an undoped AlGaAsetching stopper layer 3 formed on the n⁺-type GaAs contact layer 2, ann⁻-type GaAs layer 4 formed on the i-type AlGaAs etching stopper layer3, an anode electrode 5 formed on the n⁻-type GaAs layer 4, and acathode electrode 6 formed on the n⁺-type GaAs contact layer 2. Notethat a Schottky barrier SB is generated at an interface between theanode electrode 5 and the n⁻-type GaAs layer 4.

[0051] In the Schottky barrier diode SBD of FIG. 4, when a forward biasvoltage is applied to the anode electrode 5 and the cathode electrode 6,a current as indicated by an arrow I flows from the anode electrode 5 tothe n⁻-type GaAs layer 4 perpendicular to the surface of the n⁻-typeGaAs layer 4, and then, the current I flows from the n⁻-type GaAs layer4 via the i-type AlGaAs etching stopper layer 3 and the n⁺-type GaAscontact layer 2 to the cathode electrode 6 in parallel with the surfaceof the nt-type GaAs contact layer 2.

[0052] In the Schottky barrier diode SBD of FIG. 4, although the path ofthe current I adjacent to the surface of the n⁺-type GaAs contact layer2 is still close thereto, there is no surface level within the n⁺-typeGaAs contact layer 2 due to the presence of the i-type AlGaAs etchingstopper layer 3. In this case, a surface level SL may be generated inthe i-type AlGaAs etching stopper layer 3; however, the path of thecurrent I is distant from this surface level SL. Therefore, the currentI is hardly affected by the surface level SL of the i-type AlGaAsetching stopper layer 3. As a result, the low frequency noisecharacteristics of the Schottky barrier diode SBD of FIG. 4 can beimproved.

[0053] The method for manufacturing the Schottky barrier diode SBD ofFIG. 4 will be explained next with reference to FIGS. 5A through 5E.

[0054] First, referring to FIG. 5A, an n⁺-type GaAs contact layer 2, ani-type AlGaAs etching stopper layer 3 and an n⁻-type GaAs layer 4 aregrown on a semi-insulating GaAs substrate 1 by an MBE process, ametal-organic chemical vapor deposition (MOCVD) process or a vapor-phaseepitaxy (VPE) process. In this case, the i-type AlGaAs etching stopperlayer 3 is about 50 Å thick.

[0055] Next, referring to FIG. 5B; a photoresist pattern layer 11 isformed by a photolithography process. Then, the n⁻-type GaAs layer 4 isetched by a selective dry etching process using BCl₃ gas and the i-typeAlGaAs etching stopper layer 3 as an etching stopper. Then, thephotoresist pattern layer 11 is removed.

[0056] Next, referring to FIG. 5C, a photoresist pattern layer 12 isformed by a photolithography process. Then, the i-type AlGaAs etchingstopper layer 3 is etched by a wet etching process using hydrogenperoxide water and the n⁺-type GaAs layer 2 as an etching stopper. Then,the photoresist pattern layer 12 is removed.

[0057] Next, referring to FIG. 5D, a silicon oxide layer 13 is depositedby a CVD process.

[0058] Next, referring to FIG. 5E, a photoresist pattern layer 14 isformed by a photolithography process. Then, the silicon oxide layer 13is etched by a dry etching process using SF₆ gas.

[0059] Finally, an anode electrode 5 and a cathode electrode 6 areformed by a sputtering process and a lift-off process. Then, thephotoresist pattern layer 14 is removed, to obtain the Schottky barrierdiode SBD of FIG. 4. Note that the silicon oxide layer 13 is not shownin FIG. 4.

[0060] In the first embodiment, although the AlGaAs etching stopperlayer 3 is undoped, the AlGaAs etching stopper layer 3 can be doped,i.e., of an n-type.

[0061] In FIG. 6, which illustrates a second embodiment of the diodeaccording to the present invention, the anode electrode 6 and thecathode electrode 6 of FIG. 4 are buried in the n⁻-type GaAs layer 4 andthe n⁺-type GaAs contact layer 2, respectively, of FIG. 4.

[0062] In the Schottky barrier diode SBD of FIG. 6, the path of thecurrent I adjacent to the surface of the n⁺-type GaAs contact layer 2 isdistant therefrom, the path of the current I is further distant from thesurface level SL. Therefore, the current I is hardly affected by thesurface level SL of the i-type AlGaAs etching stopper layer 3. As aresult, the low frequency noise characteristics of the Schottky barrierdiode SBD of FIG. 6 can be further improved.

[0063] The method for manufacturing the Schottky barrier diode SBD ofFIG. 6 will be explained next with reference to FIGS. 7A through 7F.

[0064] The manufacturing steps as illustrated in FIGS. 7A through 7E arethe same as those as illustrated in FIGS. 5A through 5E, respectively.

[0065] After the manufacturing step as illustrated in FIG. 7E, iscarried out, referring to FIG. 7F, the n⁺-type GaAs contact layer 2 andthe n⁻-type GaAs layer 4 are etched by a wet etching process usingphosphoric acid. In this case, the etching depth of the n⁺-type GaAscontact layer 2 and the n⁻-type GaAs layer 4 is about 100 Å. Then, ananode electrode 5 and a cathode electrode 6 are formed by a sputteringprocess and a lift-off process. Then, the photoresist pattern layer 14is removed, to obtain the Schottky barrier diode SBD of FIG. 6. Notethat the silicon oxide layer 13 is not shown in FIG. 6.

[0066] Even in the second embodiment, although the AlGaAs etchingstopper layer 3 is undoped, the AlGaAs etching stopper layer 3 can bedoped, i.e., of an n-type.

[0067] In FIG. 8, which illustrates a third embodiment of the diodeaccording to the present invention, the i-type GaAs etching stopperlayer 3 of FIG. 6 is omitted.

[0068] In the Schottky barrier diode SBD of FIG. 8, the path of thecurrent I adjacent to the surface of the n⁺-type GaAs contact layer 2 isdistant therefrom, the path of the current I is distant from the surfacelevel SL within the n⁺-type GaAs contact layer 2 Therefore, the currentI is hardly affected by the surface level SL of the n⁺-type GaAs layer2.-As a result, the low frequency noise characteristics of the Schottkybarrier diode SBD of FIG. 8 can be improved.

[0069] The method for manufacturing the Schottky barrier diode SBD ofFIG. 8 will be explained next with reference to FIGS. 9A through 9E.

[0070] First, referring to FIG. 9A, an n⁺-type GaAs contact layer 2 andan n⁻-type GaAs layer 4 are grown on a semi-insulating GaAs substrate 1by an MBE process, an MOCVD process or a VPE process.

[0071] Next, referring to FIG. 9B, a photoresist pattern layer 11 isformed by a photolithography process. Then, the n⁻-type GaAs layer 4 isetched by a selective dry etching process using BCl₃ gas. Then, thephotoresist pattern layer 11 is removed.

[0072] Next, referring to FIG. 9C, a silicon oxide layer 13 is depositedby a CVD process.

[0073] Next, referring to FIG. 9D, a photoresist pattern layer 14 isformed by a photolithography process. Then, the silicon oxide layer 13is etched by a dry etching process using SF₆ gas.

[0074] Next, referring to FIG. 9E, the n⁺-type GaAs contact layer 2 andthe n⁻-type GaAs layer 4 are etched by a wet etching process usingphosphoric acid. In this case, the etching depth of the n⁺-type GaAscontact layer 2 and the n⁻-type GaAs layer 4 is about 100 Å. Then, ananode electrode 5 and a cathode electrode 6 are formed by a sputteringprocess and a lift-off process. Then, the photoresist pattern layer 14is removed, to obtain the Schottky barrier diode SBD of FIG. 8. Notethat the silicon oxide layer 13 is not shown in FIG. 8.

[0075] In FIG. 10, which illustrates a fourth embodiment of the diodeaccording to the present invention that is, in this case, a Schottkybarrier diode SBD, an i-type GaAs layer 21 and an i-type AlGaAs etchingstopper layer 22 are added to the Schottky barrier diode SBD of FIG. 4.

[0076] In the Schottky barrier diode SBD of FIG. 10, a surface level SLmay be generated in the i-type AlGaAs etching stopper layer 22; however,the path of the current I is far away from this surface level SL.Therefore, the current I is hardly affected by the surface level SL ofthe i-type AlGaAs etching stopper layer 22. As a result, the lowfrequency noise characteristics of the Schottky barrier diode SBD ofFIG. 10 can be further improved.

[0077] The method for manufacturing the Schottky barrier diode SBD ofFIG. 10 will be explained next with reference to FIGS. 11A through 11E.

[0078] First, referring to FIG. 11A, an n⁺-type GaAs contact layer 2, ani-type AlGaAs etching stopper layer 3, an i-type GaAs layer 21, ani-type AlGaAs etching stopper layer 22 and an n⁻-type GaAs layer 4 aregrown on a semi-insulating substrate 1 by an MBE process, an MOCVDprocess or a VPE process. In this case, the i-type AlGaAs etchingstopper layers 3 and 22 are about 50 Å thick.

[0079] Next, referring to FIG. 11A, in the same way as in FIG. 5B, aphotoresist pattern layer 11 is formed by a photolithography process.Then, the n⁻-type GaAs layer 4 is etched by a 1 selective dry etchingprocess using BCl₃ gas and the i-type AlGaAs etching stopper layer 22 asan etching stopper. Then, the photoresist pattern layer 11 is removed.

[0080] Next, referring to FIG. 11C, a photoresist pattern layer 12 isformed by a photolithography process. Then, the i-type AlGaAs etchingstopper layer 22 is etched by a wet etching process using hydrogenperoxide water and the i-type GaAs layer 21 as an etching stopper. Then,the i-type GaAs layer 21 is etched by a 1 selective dry etching processusing BCl₃ gas and the i-type AlGaAs etching stopper layer 3 as anetching stopper. Then, the i-type AlGaAs etching stopper layer 3 isetched by a wet etching process using hydrogen peroxide water and then⁺-type GaAs layer 3 as an etching stopper. Then, the photoresistpattern layer 12 is removed.

[0081] Next, referring to FIG. 11D, in the same way as in FIG. 5D, asilicon oxide layer 13 is deposited by a CVD process.

[0082] Next, referring to FIG. 11E, in the same way as in FIG. 5E, aphotoresist pattern layer 14 is formed by a photolithography process.Then, the silicon oxide layer 13 is etched by a dry etching processusing SF₆ gas.

[0083] Finally, an anode electrode 5 and a cathode electrode 6 areformed by a sputtering process and a lift-off process. Then, thephotoresist pattern layer 14 is removed, to obtain the Schottky barrierdiode SBD of FIG. 10. Note that the silicon oxide layer 13 is not shownin FIG. 10.

[0084] In the fourth embodiment, although the AlGaAs etching stopperlayers 3 and 22 are undoped, the AlGaAs etching stopper layers 3 and 22can be doped, i.e., of an n-type.

[0085] In the fourth embodiment, the cathode electrode 6 can be buriedin the n⁺-type GaAs contact layer 2 in the same way as in the thirdembodiment, so as to further improve the low frequency noisecharacteristics.

[0086] In FIG. 12, which illustrates a fifth embodiment of the diodeaccording to the present invention that is, in this case, a tunnel diodeTD, the tunnel diode TD is of a vertical type which is constructed by asemi-insulating GaAs substrate 1, an n⁺-type GaAs contact layer 2 formedon the GaAs substrate 1, an undoped AlGaAs etching stopper layer 3formed on the n⁺-type GaAs contact layer 2, an n⁺-type GaAs layer 31formed on the i-type AlGaAs etching stopper layer 3, a p⁺-type GaAslayer 32 formed on the n⁺-type GaAs layer 31, an anode electrode 5formed on the p⁺-type GaAs layer 32, and a cathode electrode 6 formed onthe n⁺-type GaAs contact layer 2.

[0087] In the tunnel diode TD of FIG. 12, when a forward bias voltage isapplied to the anode electrode 5 and the cathode electrode 6, a currentas indicated by an arrow I flows from the anode electrode 5 via thep⁺-type GaAs layer 32 to the n⁺-type GaAs layer 31 perpendicular tothe-surface thereof, and then, the current I flows from the n⁺-type GaAslayer 31 via the i-type AlGaAs etching stopper layer 3 and the n⁺-typeGaAs contact layer 2 to the cathode electrode 6 in parallel with thesurface of the n⁺-type GaAs contact layer 2.

[0088] Even in the tunnel diode TD of FIG. 12, although the path of thecurrent I adjacent to the surface of the n⁺-type GaAs contact layer 2 isstill close thereto, there is no surface level within the n⁺-type GaAscontact layer 2 due to the presence of the i-type AlGaAs etching stopperlayer 3. In this case, a surface level SL may be generated in the i-typeAlGaAs etching stopper layer 3; however, the path of the current I isdistant from this surface level SL. Therefore, the current I is hardlyaffected by the surface level SL of the i-type AlGaAs etching stopperlayer 3. As a result, the low frequency noise characteristics of thetunnel diode TD of FIG. 12 can be improved.

[0089] The method for manufacturing the tunnel diode TD of FIG. 12 willbe explained next with reference to FIGS. 13A through 13E.

[0090] First, referring to FIG. 13A, an n⁺-type GaAs contact layer 2, ani-type AlGaAs etching stopper layer 3, an n⁺-type GaAs layer 31, ap⁺-type GaAs layer 32 and an n⁻-type GaAs layer 4 are grown on asemi-insulating substrate 1 by an MBE process, an MOCVD process or a VPEprocess. In this case, the i-type AlGaAs etching stopper layer 3 isabout 50 Å thick.

[0091] Next, referring to FIG. 13B, a photoresist pattern layer 11 isformed by a photolithography process. Then, the p⁺-type GaAs layer 32and the n⁺-type GaAs layer 31 are etched by a 1 selective dry etchingprocess using BCl₃ gas and the i-type AlGaAs etching stopper layer 3 asan etching stopper. Then, the photoresist pattern layer 11 is removed.

[0092] Next, referring to FIG. 13C, in the same way as in FIG. SC, aphotoresist pattern layer 12 is formed by a photolithography process.Then, the i-type AlGaAs etching stopper layer 3 is etched by a wetetching process using hydrogen peroxide water and the nt-type GaAs layer2 as an etching stopper. Then, the photoresist pattern layer 12 isremoved.

[0093] Next, referring to FIG. 13D, in the same way as in FIG. 5D, asilicon oxide layer 13 is deposited by a CVD process.

[0094] Next, referring FIG. 13E in the same way as in to FIG. 5E, aphotoresist pattern layer 14 is formed by a photolithography process.Then, the silicon oxide layer 13 is etched by a dry etching processusing SF₆ gas.

[0095] Finally, an anode electrode 5 and a cathode electrode 6 areformed by a sputtering process and a lift-off process. Then, thephotoresist pattern layer 14 is removed, to obtain the tunnel diode TDof FIG. 12. Note that the silicon oxide layer 13 is not shown in FIG.12.

[0096] In the fifth embodiment, although the AlGaAs etching stopperlayer 3 is undoped, the AlGaAs etching stopper layer 3 can be doped,i.e., of an n-type.

[0097] In the fourth embodiment, the cathode electrode 6 can be buriedin the n⁺-type GaAs contact layer 2 in the same way as in the thirdembodiment, so as to further improve the low frequency noisecharacteristics.

[0098] In FIG. 14, which illustrates a sixth embodiment of the diodeaccording to the present invention that is, in this case, a PIN diode D,the PIN diode D is of a vertical type which is constructed by asemi-insulating GaAs substrate 1, an n⁺-type GaAs contact layer 2 formedan the GaAs substrate 1, an undoped AlGaAs etching stopper layer 3formed on the n⁺-type GaAs contact layer 2, an n-type GaAs layer 41formed on the i-type AlGaAs etching stopper layer 3, an i-type GaAslayer 42 formed on the n-type GaAs layer 41 a p-type GaAs layer 43formed on the i-type GaAs layer 42, an anode electrode 5 formed on thep-type GaAs layer 43, and a cathode electrode 6 formed on the n⁺-typeGaAs contact layer 2.

[0099] In the PIN diode D of FIG. 14, when a forward bias voltage isapplied to the anode electrode 5 and the cathode electrode 6, a currentas indicated by an arrow I flows from the anode electrode 5 via thep-type GaAs layer 43 and the i-type GaAs layer 42 to the n-type GaAslayer 41 perpendicular to the surface thereof, and then, the current Iflows from the n-type GaAs layer 41 via the i-type AlGaAs etchingstopper layer 3 and the n⁺-type GaAs contact layer 2 to the cathodeelectrode 6 in parallel with the surface of the n⁺-type GaAs contactlayer 2.

[0100] Even in the PIN diode D of FIG. 14, although the path of thecurrent I adjacent to the surface of the n⁺-type GaAs contact layer 2 isstill close thereto, there is no surface level within the n⁺-type GaAscontact layer 2 due to the presence of the i-type AlGaAs etching stopperlayer 3. In this case, a surface level SL may be generated in the i-typeAlGaAs etching stopper layer 3; however, the path of the current I isdistant from this surface level SL. Therefore, the current I is hardlyaffected by the surface level SL of the i-type AlGaAs etching stopperlayer 3. As a result, the low frequency noise characteristics of the PINdiode D of FIG. 14 can be improved.

[0101] The method for manufacturing the tunnel diode D of FIG. 14 willbe explained next with reference to FIGS. 15A through 15E.

[0102] First, referring to FIG. 15A, an n⁺-type GaAs contact layer 2, ani-type AlGaAs etching stopper layer 3, an n-type GaAs layer 41, ani-type GaAs layer 42 a p-type GaAs layer 43 and an n⁻-type GaAs layer 4are grown on a semi-insulating substrate 1 by an MBE process, an MOCVDprocess or a VPE process. In this case, the i-type AlGaAs etchingstopper layer 3 is about 50 Å thick.

[0103] Next, referring to FIG. 15B, a photoresist pattern layer 11 isformed by a photolithography process. Then, the p-type GaAs layer 43,the i-type GaAs layer 42 and the n-type GaAs layer 41 are etched by a 1selective dry etching process using BCl₃ gas and the i-type AlGaAsetching stopper layer 3 as an etching stopper. Then, the photoresistpattern layer 11 is removed.

[0104] Next, referring to FIG. 15C, in the same way as in FIG. 5C, aphotoresist pattern layer 12 is formed by a photolithography process.Then, the i-type AlGaAs etching stopper layer 3 is etched by a wetetching process using hydrogen peroxide water and the nt-type GaAs layer2 as an etching stopper. Then, the photoresist pattern layer 12 isremoved.

[0105] Next, referring to FIG. 15D, in the same way as in FIG. 5D, asilicon oxide layer 13 is deposited by a CVD process.

[0106] Next, referring FIG. 15E in the same way as in to FIG. 5E, aphotoresist pattern layer 14 is formed by a photolithography process.Then, the silicon oxide layer 13 is etched by a dry etching processusing SF₆ gas.

[0107] Finally, an anode electrode 5 and a cathode electrode 6 areformed by a sputtering process and a lift-off process. Then, thephotoresist pattern layer 14 is removed, to obtain the PIN diode D ofFIG. 14. Note that the silicon oxide layer 13 is not shown in FIG. 14.

[0108] In the sixth embodiment, although the AlGaAs etching stopperlayer 3 is undoped, the AlGaAs etching stopper layer 3 can be doped,i.e., of an n-type.

[0109] In the sixth embodiment, the cathode electrode 6 can be buried inthe n⁺-type GaAs contact layer 2 in the same way as in the thirdembodiment, so as to further improve the low frequency noisecharacteristics.

[0110]FIG. 16 is a cross-sectional view illustrating a semiconductordevice in which the Schottky diode SBD of FIG. 6 is combined with a highelectron mobility transistor HEMT.

[0111] In FIG. 16, an i-type InGaAs channel layer 51 and an n-typeAlGaAs electron supply layer 52 are formed on the GaAs substrate 1 forthe high electron mobility transistor HEMT. In this case, the i-typeInGaAs channel layer 51 and the n-type AlGaAs electron supply layer 52are meaningless for the Schottky barrier diode SBD. Also, the Schottkybarrier diode SBD and the high electron mobility transistor HEMT areisolated from each other by a p⁺-type isolation region 53. Further, agate electrode 5(G) is made of the same material as the anode electrode5(A), and a source electrode 6(S) and a drain electrode 6(D) are made ofthe same material as the cathode electrode 6(C).

[0112] The method for manufacturing the semiconductor device of FIG. 16will be explained next with reference to FIGS. 17A through 17H.

[0113] First, referring to FIG. 17A, an i-type InGaAs channel layer 51,an n-type AlGaAs electron supply layer 52, an n⁺-type GaAs contact layer2, an i-type AlGaAs etching stopper layer 3 and an n⁻-type GaAs layer 4are grown on a semi-insulating GaAs substrate 1 by an MBE process, aMOCVD process or a VPE process. In this case, the i-type AlGaAs etchingstopper layer 3 is about 50 Å thick.

[0114] Next, referring to FIG. 17B, a photoresist pattern layer 11 isformed by a photolithography process. Then, the n⁻-type GaAs layer 4 isetched by a selective dry etching process using BCl₃ gas and the i-typeAlGaAs etching stopper layer 3 as an etching stopper. Then, thephotoresist pattern layer 11 is removed.

[0115] Next, referring to FIG. 17C, a photoresist pattern layer 54 isformed by a photolithography process. Then, boron ions are implantedinto the GaAs substrate 1 as well as the layers 51, 52, 2 and 3. As aresult, a p⁺-type isolation region 53 is formed. Then, the photoresistpattern 54 is removed.

[0116] Next, referring to FIG. 17D, a photoresist pattern layer 12 isformed by a photolithography process. Then, the i-type AlGaAs etchingstopper layer 3 is etched by a wet etching process using hydrogenperoxide water and the n⁺-type GaAs layer 2 as an etching stopper. Then,the photoresist pattern layer 12 is removed.

[0117] Next, referring to FIG. 17E, a photoresist pattern layer 55 isformed by a photolithography process. Then, the n⁺-type GaAs layer 2 isetched by a 1 selective dry etching process using BCl₃ gas and then-type AlGaAs etching stopper layer 52 as an etching stopper. Then, thephotoresist pattern layer 55 is removed.

[0118] Next, referring to FIG. 17F, a silicon oxide layer 13 isdeposited by a CVD process.

[0119] Next, referring to FIG. 17G, the silicon oxide layer 13 isperforated by a photolithography and dry etching process using SF₆ gasto form openings for an anode electrode 5(A) and a gate electrode 5(G).Then, the anode electrode 5(A) and the gate electrode 5(G) are buried inthe openings by a sputtering and lift-off process.

[0120] Next, referring to FIG. 17H, the silicon oxide layer 13 isperforated by a photolithography and dry etching process using SF₆ gasto form openings for a cathode electrode 6(C), a source electrode 6(G),6(S) and a drain electrode 6(D). Then, the n⁺-type GaAs contact layer 2is etched by a wet etching process using phosphoric acid. In this case,the etching depth of the n⁺-type GaAs contact layer 2 is about 100 Å.Then, the cathode electrode 6(C), the source electrode 6(C) and thedrain electrode 6(D) are buried in the openings by a sputtering andlift-off process, to obtain the semiconductor device of FIG. 16.

[0121] In FIG. 16, although the AlGaAs etching stopper layer 3 isundoped, the AlGaAs etching stopper layer 3 can be doped, i.e., of ann-type. Also, the anode electrode 5(A) can be buried in the n⁻-type GaAslayer 4, and the gate electrode 5(G) can be buried in the n-type AlGaAslayer 52.

[0122]FIG. 18 is a cross-sectional view illustrating a semiconductordevice in which the Schottky diode SBD of FIG. 6 is combined with aheterojunction bipolar transistor HBT.

[0123] In FIG. 18, the InGaAs etching stopper layer 3 is of an n-type.Also, the n⁺-type GaAs contact layer 2 of the heterojunction bipolartransistor HBT serves as a collector contact layer, and the n-type GaAslayer 3 and the n-type GaAs layer 4 serve as a collector layer.

[0124] Additionally, the heterojunction bipolar transistor HBT isconstructed by a p⁺-type GaAs base layer 61, an n-type AlGaAs emitterlayer 62 and a n⁺-type InGaAs emitter cap layer 63. Further, referencenumeral 6(C′) designates a collector electrode, 65 designates a baseelectrode, and 66 designates an emitter electrode. The collectorelectrode 6(C′) are made of the same material as the cathode electrode6(C).

[0125] The method for manufacturing the semiconductor device of FIG. 18will be explained next with reference to FIGS. 19A through 19I.

[0126] First, referring to FIG. 19A, an n⁺-type GaAs contact layer 2, ann-type AlGaAs etching stopper layer 3, an n⁻-type GaAs layer 4, ap⁺-type GaAs base layer 61, an n-type AlGaAs emitter layer 62, and ann⁺-type InGaAs emitter cap layer 63 are grown on a semi-insulating GaAssubstrate 1 by an MBE process, a MOCVD process or a CVE process. In thiscase, the n-type AlGaAs etching stopper layer 3 is about 50 Å thick.

[0127] Next, referring to FIG. 19B, a photoresist pattern layer (notshown) is formed by a photolithography process to cover an emitter area.Then, the n⁺-type InGaAs emitter cap layer 63 and the n-AlGaAs emitterlayer 62 are etched by a wet or dry etching process using thephotoresist pattern as a mask.

[0128] Next, referring to FIG. 19C, a photoresist pattern layer (notshown) is formed by a photolithography process to cover a base area andan anode area. Then, the p⁺-type GaAs layer 61 and the n⁻-GaAs layer 4are etched by a selective dry etching process using BCl₃ gas and thephotoresist pattern as a mask.

[0129] Next, referring to FIG. 19D, a photoresist pattern layer (notshown) is formed by a photolithography process to cover an area adjacentto the anode area. Then, the n-type InGaAs etching stopper layer 3 isetched by a wet etching process using hydrogen peroxide water.

[0130] Next, referring to FIG. 19E, a photoresist pattern layer (notshown) is formed by a photolithography process to cover an area otherthan the anode area. Then, the p⁺-type GaAs layer 61 of the anode areais etched by a selective dry etching process using BCl₃ gas and thephotoresist pattern layer as a mask.

[0131] Next, referring to FIG. 19F, a photoresist patter layer (notshown) is formed by a photolithography process to cover an area wherethe Schottky barrier diode SBD and the heterojunction bipolar transistorHBT will be formed. Then, the n⁺-type GaAs contact layer 2 and the GaAssubstrate 1 are etched by using the photoresist pattern layer as a mask.

[0132] Next, referring to FIG. 19G, a silicon oxide layer 13 isdeposited by a CVD process.

[0133] Next, referring to FIG. 19H, the silicon oxide layer 13 isperforated by a photolithography and dry etching process using SF₆ gasto form openings for an anode electrode 5(A), a base electrode 65 and anemitter electrode 66. Then, the anode electrode 5(A), the base electrode65 and the emitter electrode 66 are buried in the openings by asputtering and lift-off process.

[0134] Next, referring to FIG. 19I, the silicon oxide layer 13 isperforated by a photolithography and dry etching process using SF₆ gasto form openings for a cathode electrode 6(C) and a collector electrode6(C′). Then, the n⁺-type GaAs contact layer 2 is etched by a wet etchingprocess using phosphoric acid. In this case, the etching depth of then⁺-type GaAs contact layer 2 is about 100 Å. Then, the cathode electrode6(C) and the collector electrode 6(C′) are buried in the openings by asputtering and lift-off process, to obtain the semiconductor device ofFIG. 18.

[0135] In FIG. 18, the anode electrode 5(A) can be buried in the n⁻-typeGaAs layer 4, the base electrode 65 can be buried in the p⁺-type GaAsbase layer 61, and the emitter electrode 66 can be buried in the n⁺-typeInGaAs emitter cap layer 63.

[0136]FIG. 20 is a cross-sectional view illustrating a semiconductordevice in which the Schottky diode SBD of FIG. 6 is combined with a highelectron mobility transistor HEMT and a heterojunction bipolartransistor HBT.

[0137] In FIG. 20, the semiconductor device of FIG. 16 and thesemiconductor device of FIG. 18 are combined altogether. In this case,the i-type InGaAs channel layer 51 and the n-type AlGaAs electron supplylayer 52 are also formed in the heterojunction bipolar transistor HBT,however, the i-type InGaAs channel layer 51 and the n-type AlGaAselectron supply layer 52 are meaningless for the heterojunction bipolartransistor HBT.

[0138] In order to manufacture the semiconductor device of FIG. 20, oneeptaxial layer is grown on the GaAs substrate 1. That is, as illustratedin FIG. 21, an i-type InGaAs channel layer 51, an n-type AlGaAs electronsupply layer 52, an n⁺-type GaAs contact layer 2, an n-type AlGaAsetching stopper layer 3, an n⁺-type GaAs layer 4, a p⁺-type GaAs baselayer 61, an n-type AlGaAs emitter layer 62, and an n⁺-type InGaAsemitter cap layer 63 are grown on a semi-insulating GaAs substrate 1 byan MBE process, a MOGVD process or a VPE process. In this case, then-type AlGaAs etching stopper layer 3 is about 50 Å thick.

[0139] Other manufacturing steps of the semiconductor device of FIG. 20are similar to those of the semiconductor device of FIG. 18.

[0140] In FIGS. 16, 18 and 20, since an epitaxial growing process iscarried out only once, no deep trap level is generated, which wouldimprove the low frequency noise characteristics. Also, the manufacturingcost would be decreased. Further, the characteristics among wafers andamong lots hardly fluctuate, which would increase the manufacturingyield.

[0141] In FIG. 16, 18 and 20, although the Schottky barrier diode ofFIG. 6 is combined with a high electron mobility transistor HEMT and/ora heterojunction bipolar transistor HBT, the Schottky barrier diode SBDof FIGS. 4 and 7, the tunnel diode TD of FIG. 8 and the PIN diode ofFIG. 10 can be combined with a high electron mobility transistor HEMTand/or a heterojunction bipolar transistor HBT.

[0142] As explained hereinabove, according to the present invention,since the path of a current is distant from the surface level whichwould generate low frequency noise, the low frequency characteristicscan be improved.

1. A semiconductor device comprising: a semiconductor substrate; a firstsemiconductor layer formed on said semiconductor substrate; a secondsemiconductor layer formed on a part of said first semiconductor layer;a third semiconductor layer formed on a part of said secondsemiconductor layer; a first electrode formed on said thirdsemiconductor layer; and a second electrode formed on said firstsemiconductor layer in contact with said second semiconductor layer andapart from said third semiconductor layer; thus forming a diode.
 2. Thesemiconductor device as set forth in claim 1, wherein said first andthird semiconductor layers are of one conductivity type, and said secondsemiconductor layer is undoped, so that said diode is a Schottky barrierdiode.
 3. The semiconductor device as set forth in claim 1, wherein saidfirst, second and third semiconductor layers are of one conductivitytype, so that said diode is a Schottky barrier diode.
 4. Thesemiconductor device as set forth in claim 1, wherein said first andthird semiconductor layers have a different material from that of saidsecond semiconductor layer.
 5. The semiconductor device as set forth inclaim 1, wherein said second electrode is buried in said firstsemiconductor layer.
 6. The semiconductor device as set forth in claim1, further comprising: a fourth semiconductor layer formed on saidsecond semiconductor layer; and a fifth semiconductor layer formed onsaid fourth semiconductor layer, said second and fifth semiconductorlayers being made of a material different from that of said first, thirdand fourth semiconductor layers.
 7. The semiconductor device as setforth in claim 1, further comprising a fourth semiconductor layer formedon said third semiconductor layer, said first and third semiconductorlayers being of a first conductivity type, said fourth semiconductorlayer being a second conductivity type opposite to said firstconductivity type, so that said diode is a tunnel diode.
 8. Thesemiconductor device as set forth in claim 6, wherein said secondsemiconductor layer is undoped.
 9. The semiconductor device as set forthin claim 6, wherein said second semiconductor layer is of said firstconductivity type.
 10. The semiconductor device as set forth in claim 1,further comprising: a fourth semiconductor layer of an i-typeconductivity type formed on said third semiconductor layer; and a fifthsemiconductor layer formed on said fourth semiconductor layer, saidfirst and third semiconductor layers being of a first conductivity type,said fifth semiconductor layer being of a second conductivity typeopposite to said first conductivity type, so that said diode is a PINdiode.
 11. The semiconductor device as set forth in claim 10, whereinsaid second semiconductor layer is undoped.
 12. The semiconductor deviceas set forth in claim 10, wherein said second semiconductor layer is ofsaid first conductivity type.
 13. The semiconductor device as set forthin claim 1, further comprising: an i-type channel layer between saidsemiconductor substrate and said first semiconductor layer; and a chargesupply layer formed between said i-type channel layer and said firstsemiconductor layer, said i-type channel layer, said charge supply layerand said first semiconductor layer forming a heterojunction field effecttransistor separated from said diode.
 14. The semiconductor device asset forth in claim 13, wherein said diode and said field effecttransistor are separated by an isolation region therebetween in saidi-type channel layer and said charge supply layer.
 15. The semiconductordevice as set forth in claim 1, further comprising; a semiconductor baselayer having a conductivity type opposite to that of said thirdsemiconductor layer formed on said third semiconductor layer; asemiconductor emitter layer having the same conductivity type as that ofsaid third semiconductor layer formed on said semiconductor base layer;and a semiconductor emitter cap layer having the same conductivity typeas that of said third semiconductor layer formed on said semiconductoremitter layer; said first, second and third semiconductor layers, saidsemiconductor base layer, said semiconductor emitter layer and saidsemiconductor emitter cap layer forming a heterojunction bipolartransistor separated from said diode.
 16. The semiconductor device asset forth in claim 15, wherein said diode and said bipolar transistorare separated by a groove formed in said first semiconductor layer andsaid semiconductor substrate.
 17. A semiconductor device comprising: asemiconductor substrate; a first semiconductor layer formed on saidsemiconductor substrate; a second semiconductor layer formed on a partof said first semiconductor layer; a first electrode formed on saidsecond semiconductor layer; and a second electrode buried in said firstsemiconductor layer and apart from said second semiconductor layer, thusforming a diode.
 18. The semiconductor device as set forth in claim 17,wherein said first and second semiconductor layers are of oneconductivity type, so that said diode is a Schottky barrier diode. 19.The semiconductor device as set forth in claim 17, further comprising: athird semiconductor layer formed on said first semiconductor layer; anda fourth semiconductor layer formed on said third semiconductor layer,said second and fourth semiconductor layers being made of a materialdifferent from that of said first, second and third semiconductorlayers.
 20. The semiconductor device as set forth in claim 17, furthercomprising a third semiconductor layer formed on said secondsemiconductor layer, said first and second semiconductor layers being ofa first conductivity type, said third semiconductor layer being a secondconductivity type opposite to said first conductivity type, so that saiddiode is a tunnel diode.
 21. The semiconductor device as set forth inclaim 17, further comprising: a third semiconductor layer of an i-typeconductivity type second on said second semiconductor layer; and afourth semiconductor layer formed on said third semiconductor layer,said first and second semiconductor layers being of a first conductivitytype, said fourth semiconductor layer being of a second conductivitytype opposite to said first conductivity type, so that said diode is aPIN diode.
 22. The semiconductor device as set forth in claim 17,further comprising: an i-type channel layer between said semiconductorsubstrate and said first semiconductor layer; and a charge supply layerformed between said i-type channel layer and said first semiconductorlayer, said i-type channel layer, said charge supply layer and saidfirst semiconductor layer forming a heterojunction field effecttransistor separated from said diode.
 23. The semiconductor device asset forth in claim 22, wherein said diode and said field effecttransistor are separated by an isolation region therebetween in saidi-type channel layer and said charge supply layer.
 24. The semiconductordevice as set forth in claim 17, further comprising: a semiconductorbase layer having a conductivity type opposite to that of said thirdsemiconductor layer formed on said second semiconductor layer; asemiconductor emitter layer having the same conductivity type as that ofsaid second semiconductor layer formed on said semiconductor base layer;and a semiconductor emitter cap layer having the same conductivity typeas that of said second semiconductor layer formed on said semiconductoremitter layer, said first and second semiconductor layers, saidsemiconductor base layer, said semiconductor emitter layer and saidsemiconductor emitter cap layer forming a heterojunction bipolartransistor separated from said diode.
 25. The semiconductor device asset forth in claim 24, wherein said diode and said bipolar transistorare separated by a groove formed in said first semiconductor layer andsaid semiconductor substrate.
 26. A method for manufacturing asemiconductor device, comprising the steps of: forming first, second andthird semiconductor layers on a semiconductor substrate by an epitaxialgrowing process; patterning said third semiconductor layer by an etchingprocess using said second semiconductor layer as an etching stopper;patterning said second semiconductor layer by an etching process usingsaid first semiconductor layer as an etching stopper, so that said thirdsemiconductor layer is formed on a part of said second semiconductorlayer; forming a first electrode on said third semiconductor layer; andforming a second electrode on said first semiconductor layer adjacent tosaid second semiconductor layer and apart from said third semiconductorlayer, thus completing a diode.
 27. The method as set forth in claim 26,wherein said first and third semiconductor layers are of oneconductivity type, and said second semiconductor layer is undoped, sothat said diode is a Schottky barrier diode.
 28. The method as set forthin claim 26, wherein said first, second and third semiconductor layersare of one conductivity type, so that said diode is a Schottky barrierdiode.
 29. The method as set forth in claim 26, wherein said first andthird semiconductor layers have a different material from that of saidsecond semiconductor layer.
 30. The method as set forth in claim 27,further comprising a step of partly etching said first semiconductorlayer after said second semiconductor layer is patterned and before saidsecond electrode is formed, so that said second electrode is buried insaid first semiconductor layer.
 31. The method as set forth in claim 27,wherein said epitaxial growing step further forms a fourth semiconductorlayer and a fifth semiconductor layer between said second and fourthsemiconductor layers, said second and fifth semiconductor layers beingmade of a material different from that of said first, third and fourthsemiconductor layers.
 32. The method as set forth in claim 27, whereinsaid epitaxial growing step further forms a fourth semiconductor layeron said third semiconductor layer, said first and third semiconductorlayers being of a first conductivity type, said fourth semiconductorlayer being a second conductivity type opposite to said firstconductivity type, so that said diode is a tunnel diode.
 33. The methodas set forth in claim 31, wherein said second semiconductor layer isundoped.
 34. The method as set forth in claim 31, wherein said secondsemiconductor layer is of said first conductivity type.
 35. The methodas set forth in claim 26, wherein said epitaxial growing step furtherforms a fourth semiconductor layer of an i-type conductivity type and afifth semiconductor layer on said fourth semiconductor layer, said firstand third semiconductor layers being of a first conductivity type, saidfifth semiconductor layer being of a second conductivity type oppositeto said first conductivity type, so that said diode is a PIN diode. 36.The method as set forth in claim 35, wherein said second semiconductorlayer is undoped.
 37. The method as set forth in claim 35, wherein saidsecond semiconductor layer is of said first conductivity type.
 38. Themethod as set forth in claim 26, wherein said epitaxial growing stepfurther forms an i-type channel layer and a charge supply layer betweensaid semiconductor substrate and said first semiconductor layer, saidi-type channel layer, said charge supply layer and said firstsemiconductor layer forming a heterojunction field effect transistorseparated from said diode.
 39. The method as set forth in claim 38,further comprising a step of forming an isolation region in said i-typechannel layer and said charge supply layer, so that said diode and saidfield effect transistor are separated by said isolation region.
 40. Themethod as set forth in claim 26, wherein said epitaxial growing stepfurther forms a semiconductor base layer having a conductivity typeopposite to that of said third semiconductor layer; a semiconductoremitter layer having the same conductivity type as that of said thirdsemiconductor layer, and a semiconductor emitter cap layer having thesame conductivity type as that of said third semiconductor layer on saidthird semiconductor layer; said first, second and third semiconductorlayers, said semiconductor base layer, said semiconductor emitter layerand said semiconductor emitter cap layer forming a heterojunctionbipolar transistor separated from said diode.
 41. The method as setforth in claim 40, further comprising a step of forming a groove in saidfirst semiconductor layer and said semiconductor substrate, so that saiddiode and said bipolar transistor are separated by said groove.
 42. Amethod for manufacturing a semiconductor device, comprising the stepsof: forming first and second semiconductor layers on a semiconductorsubstrate by an epitaxial growing process substrate; patterning saidsecond semiconductor layer so that said second semiconductor layer isformed on a part of said first semiconductor layer; partly etching saidfirst semiconductor layer after said second semiconductor layer ispatterned; forming a first electrode on said second semiconductor layer;and burying a second electrode in said first semiconductor layer andapart from said second semiconductor layer, thus forming a diode. 43.The method as set forth in claim 32, wherein said first and secondsemiconductor layers are of one conductivity type, so that said diode isa Schottky barrier diode.
 44. The method as set forth in claim 42,wherein said epitaxial growing step further forms a third semiconductorlayer and a fourth semiconductor layer between said first and thirdsemiconductor layers, said third semiconductor layer being made of amaterial different from that of said first and second semiconductorlayers.
 45. The method as set forth in claim 42, wherein said epitaxialprocess further forms a third semiconductor layer on said secondsemiconductor layer, said first and second semiconductor layers being ofa first conductivity type, said third semiconductor layer being a secondconductivity type opposite to said first conductivity type, so that saiddiode is a tunnel diode.
 46. The method as set forth in claim 42,wherein said epitaxial growing step further forms a third semiconductorlayer of an i-type conductivity type and a fourth semiconductor layer onsaid second semiconductor layer, said first and second semiconductorlayers being of a first conductivity type, said fourth semiconductorlayer being of a second conductivity type opposite to said firstconductivity type, so that said diode is a PIN diode.
 47. The method asset forth in claim 42, wherein said epitaxial growing step further formsan i-type channel layer and a charge supply layer between said firstsemiconductor substrate and said first semiconductor layer, said i-typechannel layer, said charge supply layer and said first semiconductorlayer forming a field effect transistor having hetero junctionsseparated from said diode.
 48. The method as set forth in claim 47,further comprising a step of forming an isolation region in said i-typechannel layer and said charge supply layer, so that said diode and saidfield effect transistor are separated by said isolation region.
 49. Themethod as set forth in claim 42, wherein said epitaxial growing stepfurther forms a semiconductor base layer having a conductivity typeopposite to that of said third semiconductor layer, a semiconductoremitter layer having the same conductivity type as that of said secondsemiconductor layer, and a semiconductor emitter cap layer having thesame conductivity type as that of said second semiconductor layer onsaid second semiconductor layer, said first and second semiconductorlayers, said semiconductor base layer, said semiconductor emitter layerand said semiconductor emitter cap layer forming a heterojunctionbipolar transistor separated from said diode.
 50. The method as setforth in claim 49, further comprising a step of forming a groove formedin said first semiconductor layer and said semiconductor substrate, sothat said diode and said bipolar transistor are separated by saidgroove.